1. Field of the Invention
The present invention relates to semiconductor memory devices, and, more particularly, to circuits for controlling a voltage power peak (VPP) level, which is a high voltage used in a semiconductor memory device.
2. Description of the Related Art
Because the VPP voltage of semiconductor devices, such as memory devices, is typically higher than an external voltage source (VDD), the VPP voltage may compensate for a loss of threshold voltage in transistors. In this regard, the VPP voltage is commonly used in semiconductor devices. In particular, the VPP voltage is often used in memory devices as a wordline voltage.
A VPP voltage level may be determined by the amount of electric charge of a VPP capacitor. Electric charge of a VPP capacitor may be lost by minute reverse bias leakage current flowing in a PN junction of the VPP capacitor and by a large transient current used to drive circuits within semiconductor memory chips whenever the semiconductor memory chips are activated. Thus, the VPP voltage level may not be consistently maintained unless such a loss of electric charge is compensated for.
To maintain a relatively consistent VPP voltage level, a semiconductor device may use a VPP voltage level detector. If the VPP voltage is lowered due to the leakage of electric charge, the VPP voltage level detector may detect the lowered VPP voltage and turn on an oscillator to raise the level of the lowered VPP voltage. Then, the VPP voltage level detector may detect the level of the VPP voltage again. If the VPP voltage has been raised to a desired level, then the VPP voltage level detector turns off the oscillator.
The oscillator is activated by a package burn-in mode information (PBI) signal and changed linearly according to the VDD voltage. The PBI signal may use a test mode when the semiconductor device is in a burn-in mode.
FIG. 1 is a block diagram that illustrates a conventional voltage level shifter. The voltage level shifter is configured such that the PBI signal can be input to a VPP detection circuit 11, a VPP generation circuit 12, a Vrefa generation circuit 13, and a Vp/VBLP generation circuit 14. Here, the Vrefa voltage is a reference voltage for semiconductor memory cells, the Vp voltage is a plate voltage of the semiconductor memory cells, and the VBLP voltage is a pre-charge voltage of a bitline of a semiconductor memory. The voltage level shifter is activated by the PBI signal and controls a VPP voltage level based on test-mode register bit information.
FIG. 2 is a schematic that illustrates a conventional VPP level control circuit, which controls a VPP voltage level using mode register bit information. When in a test mode, a semiconductor device enters a mode register setting mode and sets corresponding bits such that the VPP voltage can be adjusted to a desired level. The set bits are input to first through nth MOS transistors MT1 through MTn as zero'th through (n-1)th control bits M0 through Mn-1, thus controlling the VPP voltage level.
For example, if the zero'th through (n-1)th control bits M0 through Mn-1 are 1000 through 0, then a Y amount of current can be made to flow. If the zero'th through (n-1)th control bits M0 through Mn-1 are 0100 through 0, then a 2Y amount of current can be made to flow. If the zero'th through (n−1)th control bits M0 through Mn-1 are 1100 through 0, then a 3Y amount of current can be made to flow. In other words, the VPP voltage level can be adjusted by controlling the amount of current. In this case, if the first through nth MOS transistors MT1 through MTn have different sizes, 2n types of VPP voltage levels can be set.
It is determined whether the semiconductor memory cells are defective using data of a predetermined pattern.
The VPP level control circuit of the semiconductor memory device can adjust the VPP voltage level by controlling the VDD voltage. However, if the VDD voltage changes, then so do levels of other DC voltages (Vrefa, Vp, VBLP, etc.) as well as the VPP voltage level. Changes in the levels of such voltages are illustrated in FIG. 3.
FIG. 3 is a graph illustrating the variation in levels of voltages controlled by a conventional voltage level control circuit. As the VDD voltage changes, not only the VPP voltage level but also the levels of other DC voltages, such as Vrefa, Vp, and VBLP, change accordingly. In this case, if the VDD voltage changes to raise the level of the VPP voltage, the levels of other voltages may also be affected and changed accordingly. Hence it may not be possible to control the VPP voltage level independently of the levels of other voltages using the VDD voltage.